If the operand is a byte, the processor multiplies it by the contents of AL and returns the bit result to AH and AL. If the operand is a word, the processor multiplies it by the contents of AX and returns the bit result to DX and AX.
This instruction has three variations. First has one operand and behaves in the same way as the mul instruction. Second has two operands, in this case destination operand is multiplied by the source operand and the result replaces the destination operand. Destination operand must be a general register, it can be word or double word, source operand can be general register, memory or immediate value.
Third form has three operands, the destination operand must be a general register, word or double word in size, source operand can be general register or memory, and third operand must be an immediate value. The source operand is multiplied by the immediate value and the result is stored in the destination register.
All the three forms calculate the product to twice the size of operands and set CF and OF when the upper half of the result is nonzero, but second and third form truncate the product to the size of operands. So second and third forms can be also used for unsigned operands because, whether the operands are signed or unsigned, the lower half of the product is the same.
Below are the examples for all three forms:. The dividend the accumulator is twice the size of the divisor the operand , the quotient and remainder have the same size as the divisor. If divisor is byte, the dividend is taken from AX register, the quotient is stored in AL and the remainder is stored in AH. If divisor is word, the upper half of dividend is taken from DX, the lower half of dividend is taken from AX, the quotient is stored in AX and the remainder is stored in DX.
Rules for the operand are the same as for the mul instruction. It uses the same registers as the div instruction, and the rules for the operand are the same. Decimal arithmetic is performed by combining the binary arithmetic instructions already described in the prior section with the decimal arithmetic instructions. The decimal arithmetic instructions are used to adjust the results of a previous binary arithmetic operation to produce a valid packed or unpacked decimal result, or to adjust the inputs to a subsequent binary arithmetic operation so the operation will produce a valid packed or unpacked decimal result.
The carry flag is set if carry was needed. The carry flag is set if a borrow was needed. The carry flag is set and AH is incremented if a carry is necessary.
The carry flag is set and AH decremented if a borrow is necessary. The high order digit is left in AH, the low order digit in AL. The generalized version of this instruction allows adjustment of the contents of the AX to create two unpacked digits of any number base. The standard version of this instruction has no operands, the generalized version has one operand - an immediate value specifying the number base for the created digits.
AH should contain the high order digit and AL the low order digit. This instruction adjusts the value and places the result in AL, while AH will contain zero.
The generalized version of this instruction allows adjustment of two unpacked digits of any number base. Rules for the operand are the same as for the aam instruction. It has no effect on the flags. The location of the bit is specified as an offset from the low order end of the operand. The value of the offset is the taken from the second operand, it either may be an immediate byte or a general register. These instructions first assign the value of the selected bit to CF.
The first operand can be word or double word. The bit string being scanned is specified by source operand, it may be either general register or memory. The ZF flag is set if the entire string is zero no set bits are found ; otherwise it is cleared. If no set bit is found, the value of the destination register is undefined. The destination operand can be byte, word, or double word general register or memory.
The second operand can be an immediate value or the CL register. The processor shifts zeros in from the right low order side of the operand as bits exit from the left side.
The last bit that exited is stored in CF. Rules for operands are the same as for the shl instruction. The source operand remains unmodified.
The destination operand can be a word or double word general register or memory, the source operand must be a general register, third operand can be an immediate value or the CL register. Rules for operands are the same as for the shld instruction. For each rotation specified, the high order bit that exits from the left of the operand returns at the right to become the new low order bit. For each rotation specified, the low order bit that exits from the right of the operand returns at the left to become the new high order bit.
Rules for the operands are the same as for the and instruction. This instruction is provided for converting little-endian values to big-endian format and vice versa. The destination address can be specified directly within the instruction or indirectly through a register or memory, the acceptable size of this address depends on whether the jump is near or far it can be specified by preceding the operand with near or far operator and whether the instruction is bit or bit. Operand for near jump should be word size for bit instruction or the dword size for bit instruction.
Operand for far jump should be dword size for bit instruction or pword size for bit instruction. A direct jmp instruction includes the destination address as part of the instruction and can be preceded by short , near or far operator , the operand specifying address should be the numerical expression for near or short jump, or two numerical expressions separated with colon for far jump, the first specifies selector of segment, the second is the offset within segment.
The pword operator can be used to force the bit far call, and dword to force the bit far call. An indirect jmp instruction obtains the destination address indirectly through a register or a pointer variable, the operand should be general register or memory.
See also 1. Rules for the operands are the same as for the jmp instruction, but the call has no short variant of direct instruction and thus it not optimized. These instructions default to the size of address appropriate for the current code setting, but the size of address can be forced to bit by using the retw , retnw and retfw mnemonics, and to bit by using the retd , retnd and retfd mnemonics.
All these instructions may optionally specify an immediate operand, by adding this constant to the stack pointer, they effectively remove any arguments that the calling program pushed on the stack before the execution of the call instruction.
It differs from ret in that it also pops the flags from the stack into the flags register. The flags are stored on the stack by the interrupt mechanism. It defaults to the size of return address appropriate for the current code setting, but it can be forced to use bit or bit address by using the iretw or iretd mnemonic. The conditional transfer instructions are jumps that may or may not transfer control, depending on the state of the CPU flags when the instruction executes.
The mnemonics for conditional jumps may be obtained by attaching the condition mnemonic see table 2. The conditional jumps can be short or near, and direct only, and can be optimized see 1. The loop instructions are conditional jumps that use a value placed in CX or ECX to specify the number of repetitions of a software loop. Every loop instruction needs an operand being an immediate value specifying target address, it can be only short jump in the range of bytes back and bytes forward from the address of instruction following the loop instruction.
Rules for the operands are the same as for the loop instruction. The interrupt service routine terminates with an iret instruction that returns control to the instruction that follows int.
An interrupt 5 occurs if the value contained in the register is less than the lower bound or greater than the upper bound. It needs two operands, the first operand specifies the register being tested, the second operand should be memory address for the two signed limit values. The operands can be word or dword in size. The source operand should be an immediate value in range from 0 to , or DX register. The program can specify the number of the port using the same methods as the in instruction.
The destination operand should be an immediate value in range from 0 to , or DX register. The string operations operate on one element of a string. A string element may be a byte, a word, or a double word. If DF direction flag is zero, the index registers are incremented, if DF is one, they are decremented.
The amount of the increment or decrement is 1, 2, or 4 depending on the size of the string element. Short form is obtained by attaching to the mnemonic of string operation letter specifying the size of string element, it should be b for byte element, w for word element, and d for double word element.
Size of operands can be byte, word, or double word. If the string elements are equal, ZF is set, otherwise it is cleared. The first operand for this instruction should be the source string element addressed by SI or ESI with any segment prefix, the second operand should be the destination string element addressed by DI or EDI. If the values are equal, ZF is set, otherwise it is cleared. Rules for the operand are the same as for the scas instruction.
The destination operand should be the DX register and the source operand should be memory addressed by SI or ESI with any segment prefix. When a string operation instruction has a repeat prefix, the operation is executed repeatedly, each time using a different element of the string.
The repetition terminates when one of the conditions specified by the prefix is satisfied. All three prefixes automatically decrease CX or ECX register depending whether string operation instruction uses the bit or bit addressing after each operation and repeat the associated operation until CX or ECX is zero. When these prefixes are used, repetition of the next instruction depends on the zero flag ZF also, repe and repz terminate the execution when the ZF is zero, repne and repnz terminate the execution when the ZF is set.
The flag control instructions provide a method for directly changing the state of bits in the flag register. All instructions described in this section have no operands. The contents of the remaining bits are undefined. The flags remain unaffected. The instructions obtained by attaching the condition mnemonic see table 2. The operand should be an 8-bit be general register or the byte in memory.
This instruction has no arguments. The instructions obtained by attaching the condition mnemonic to cmov mnemonic transfer the word or double word from the general register or memory to the general register only when the condition is true. The destination operand should be general register, the source operand can be general register or memory.
If the two values are equal, the source operand is loaded into the destination operand. The destination operand should be a quad word in memory. This instruction has no operands and doesn't perform any operation. This instruction is provided for software testing to explicitly generate an invalid opcode. This is instruction has no operands.
This instruction has also a short form xlatb which has no operands and uses the BX or EBX address in the segment selected by DS depending on the current code setting. The source operand must be a memory operand, and the destination operand must be a general register. The DS register receives the segment selector of the pointer while the destination register receives the offset part of the pointer.
The information returned is selected by entering a value in the EAX register before the instruction is executed. It can be used to improve the performance of spin wait loops. A leave instruction at the end of a procedure complements an enter at the beginning of the procedure to simplify stack management and to control access to variables for nested procedures.
The enter instruction includes two parameters. The first parameter specifies the number of bytes of dynamic storage to be allocated on the stack for the routine being entered. The second parameter corresponds to the lexical nesting level of the routine, it can be in range from 0 to The specified lexical level determines how many sets of stack frame pointers the CPU copies into the new stack frame from the preceding frame.
This list of stack frame pointers is sometimes called the display. The first word or double word when code is bit of the display is a pointer to the last stack frame. This pointer enables a leave instruction to reverse the action of the previous enter instruction by effectively discarding the last stack frame. After enter creates the new display for a procedure, it allocates the dynamic storage space for that procedure by decrementing ESP by the number of bytes specified in the first parameter.
To enable a procedure to address its display, enter leaves BP or EBP pointing to the beginning of the new stack frame. For nesting levels greater than zero, the processor pushes additional frame pointers on the stack before adjusting the stack pointer. The operand for both those instructions can be bit general register or memory, for smsw it can also be bit general register.
The operand should be a 6 bytes in memory. Rules for operand are the same as for the lmsw and smsw instructions. The destination operand can be a bit or bit general register. The source operand should be a bit general register or memory.
Rules for operand are the same as for the lar instruction. The operand should be a word, it can be general register or memory. If the segment is accessible and readable for verr or writable for verw the ZF flag is set, otherwise it's cleared.
Rules for operand are the same as for the lldt instruction. The first operand contains one segment selector and the second operand contains the other. If the RPL field of the destination operand is less than the RPL field of the source operand, the ZF flag is set and the RPL field of the destination operand is increased to match that of the source operand.
Otherwise, the ZF flag is cleared and no change is made to the destination operand. The destination operand can be a word general register or memory, the source operand must be a general register. In a multiprocessor environment, the bus-lock signal insures that the processor has exclusive use of any shared memory while the signal is asserted.
The lock prefix can be prepended only to the following instructions and only to those forms of the instructions where the destination operand is a memory operand: add , adc , and , btc , btr , bts , cmpxchg , cmpxchg8b , dec , inc , neg , not , or , sbb sub , xor , xadd and xchg. If the lock prefix is used with one of these instructions and the source operand is a memory operand, an undefined opcode exception may be generated. An undefined opcode exception will also be generated if the lock prefix is used with any instruction not in the above list.
The xchg instruction always asserts the bus-lock signal regardless of the presence or absence of the lock prefix. The processor determines the page that contains that address and flushes the TLB entry for that page. The processor increments the time stamp counter MSR every clock cycle and resets it to 0 whenever the processor is reset. The instruction then issues a special function bus cycle that directs external caches to also write back modified data and another bus cycle to indicate that the external caches should be invalidated.
The addresses used by these instructions are stored in MSRs. The FPU Floating-Point Unit instructions operate on the floating-point values in three formats: single precision bit , double precision bit and double extended precision bit.
The FPU registers form the stack and each of them holds the double extended precision floating-point value. When some values are pushed onto the stack or are removed from the top, the FPU registers are shifted, so ST0 is always the value on the top of FPU stack, ST1 is the first value below the top, etc.
The ST0 name has also the synonym ST. The operand can be bit, bit or bit memory location or the FPU register, it's value is then loaded onto the top of FPU register stack the ST0 register and is automatically converted into the double extended precision format. The source operand can be a bit, bit or bit memory location. The operand can be bit or bit memory location. The operand should be an bit memory location. The destination operand is always an FPU register, if the source is a memory location, the destination is ST0 register and only source operand should be specified.
An operand in memory can be a bit or bit value. When no operands are specified, ST1 is used as a destination operand. The operand should be a bit or bit memory location. All these instructions store the result in ST0 and have no operands.
The operand can be a single or double precision value in memory or the FPU register. When no operand is specified, ST1 is used as a source operand.
Rules for operands are the same as for the fcom , fcomp and fcompp , but the source operand must be an FPU register. The integer value is converted to double extended precision floating-point format before the comparision is made. The instructions obtained by attaching the FPU condition mnemonic see table 2. These instructions allow two different syntaxes, one with single operand specifying the source FPU register, and one with two operands, in that case destination operand should be ST0 register and the second operand specifies the source FPU register.
The destination operand can be either a bit memory or the AX register. The operand should be a bit memory location. All these instructions need an operand being a memory location. For each of these instructions exist two additional mnemonics that allow to precisely select the type of the operation. The fstenvw , fnstenvw , fldenvw , fsavew , fnsavew and frstorw mnemonics force the instruction to perform operation as in the bit mode, while fstenvd , fnstenvd , fldenvd , fsaved , fnsaved and frstord force the operation as in bit mode.
The operand should be an FPU register. They can operate on packed bytes eight 8-bit integers , packed words four bit integers or packed double words two bit integers , use of packed formats allows to perform operations on multiple data at one time. At least one of the operands must be a MMX register, the second one can be also a MMX register or bit memory location.
One of the operands must be a MMX register, the second one can be a general register or bit memory location. Only low double word of MMX register is used. Operation is performed on the corresponding data elements of the source and destination operand and stored in the data elements of the destination operand.
If a pair of data elements is equal, the corresponding data element in the destination operand is filled with bits of value 1, otherwise it's set to 0. Converted data elements from the source operand are stored in the high part of the destination operand, while converted data elements from the destination operand are stored in the low part. The destination operand should be a MMX register, while source operand can be a MMX register, bit memory location, or 8-bit immediate value.
The SSE extension adds more MMX instructions and also introduces the operations on packed single precision floating point values. The bit packed single precision format consists of four single precision floating point values. The bit SSE registers are designed for the purpose of operations on this data type.
At least one of the operands have to be a SSE register, the second one can be also a SSE register or bit memory location. Memory operands for movaps instruction must be aligned on boundary of 16 bytes, operands for movups instruction don't have to be aligned. One of the operands must be a SSE register, and the other operand must be a bit memory location. Both operands have to be a SSE registers.
The source operand must be a SSE register, the destination operand must be a general register. Each of the SSE arithmetic operations has two variants. When the mnemonic ends with ps , the source operand can be a bit memory location or a SSE register, the destination operand must be a SSE register and the operation is performed on packed four single precision values, for each pair of the corresponding data elements separately, the result is stored in the destination register.
When the mnemonic ends with ss , the source operand can be a bit memory location or a SSE register, the destination operand must be a SSE register and the operation is performed on single precision values, only low double words of SSE registers are used in this case, the result is stored in the low double word of destination register.
The source operand can be a bit memory location or a SSE register, the destination operand must be a SSE register. The source operand can be a bit memory location or SSE register, the third operand must be an immediate operand selecting code of one of the eight compare conditions table 2.
These two instructions have also variants with only two operands and the condition encoded within mnemonic. Their mnemonics are obtained by attaching the mnemonic from table 2.
The destination operand must be a SSE register, the source operand can be a bit memory location or SSE register, the third operand must be an 8-bit immediate value selecting which values will be moved into the destination operand.
Bits 0 and 1 select the value to be moved from destination operand to the low double word of the result, bits 2 and 3 select the value to be moved from the destination operand to the second double word, bits 4 and 5 select the value to be moved from the source operand to the third double word, and bits 6 and 7 select the value to be moved from the source operand to the high double word of the result.
The source operand can be a bit memory location or a SSE register. The source operand can be a bit memory location or MMX register. The source operand can be a bit memory location or bit general register. The source operand must be a MMX register, the destination operand must be a bit general register the high word of the destination is cleared , the third operand must an 8-bit immediate value.
The destination operand must be a MMX register, the source operand can be a bit memory location or bit general register only low word of the register is used. All these instructions follow the same rules for operands as the general MMX operations described in previous section.
The source operand must be a MMX register, the destination operand must a bit general register. The destination operand must be a MMX register, the source operand can be a bit memory location or MMX register, third operand must an 8-bit immediate value selecting which values will be moved into destination operand, in the similar way as the third operand of the shufps instruction.
The source operand should be a MMX register, the destination operand should be a bit memory location. The source operand should be a SSE register, the destination operand should be a bit memory location. Both operands should be a MMX registers, the second operand selects wich bytes from the source operand are written to memory. The operand should be an 8-bit memory location.
The memory operand for both those instructions must be aligned on 16 byte boundary, it should declare operand of no specified size. The SSE2 extension introduces the operations on packed double precision floating point values, extends the syntax of MMX instructions, and adds also some new instructions.
These instructions are analogous to movaps and movups and have the same rules for operands. These instructions are analogous to movlps and movhps and have the same rules for operands.
This instruction is analogous to movmskps and has the same rules for operands. Arithmetic operations on double precision values are: addpd , addsd , subpd , subsd , mulpd , mulsd , divpd , divsd , sqrtpd , sqrtsd , maxpd , maxsd , minpd , minsd , and they are analoguous to arithmetic operations on single precision values described in previous section. When the mnemonic ends with pd instead of ps , the operation is performed on packed two double precision values, but rules for operands are the same.
When the mnemonic ends with sd instead of ss , the source operand can be a bit memory location or a SSE register, the destination operand must be a SSE register and the operation is performed on double precision values, only low quad words of SSE registers are used in this case.
They are analoguous to SSE logical operations on single prevision values and have the same rules for operands. This instruction is analoguous to cmpps and has the same rules for operands. Variant with only two operands are obtained by attaching the condition mnemonic from table 2.
This instruction is analoguous to shufps and has the same rules for operand. Bit 0 of the third operand selects the value to be moved from the destination operand, bit 1 selects the value to be moved from the source operand, the rest of bits are reserved and must be zeroed.
They are analoguous to unpckhps and unpcklps , and have the same rules for operands. For all these instructions destination operand must be a SSE register, the source operand can be a bit memory location or SSE register.
Memory operands for movdqa instruction must be aligned on boundary of 16 bytes, operands for movdqu instruction don't have to be aligned. All MMX instructions operating on the bit packed integers those with mnemonics starting with p are extended to operate on bit packed integers located in SSE registers. The exception is pshufw instruction, which doesn't allow extended syntax, but has two new variants: pshufhw and pshuflw , which allow only the extended syntax, and perform the same operation as pshufw on the high or low quad words of operands respectively.
Also the new instruction pshufd is introduced, which performs the same operation as pshufw , but on the double words instead of words, it allows only the extended syntax. These instructions follow the same rules for operands as the general MMX operations described in 2.
The destination operand should be a SSE register, source operand should be an 8-bit immediate value. The source operand can be a bit memory location or SSE register. Rules for operand are the same. The source operand should be a bit general register, the destination operand should be a bit memory location. Both operands should be a SSE registers, the second operand selects wich bytes from the source operand are written to memory.
The destination operand has to be SSE register, the source operand must be bit memory location. All these instructions need the destination operand to be SSE register, source operand can be SSE register or bit memory location. They operate on bit or bit chunks, respectively. They operator on 8-bit, bit and bit elements respectively. If the value in source is negative, the corresponding value in the destination register is negated, if the value in source is positive, no operation is performed on the corresponding value is performed, and if the value in source is zero, the value in destination is zeroed, too.
This is the only SSSE3 instruction that takes three arguments. The 3DNow! These instructions follow the same rules as the general MMX operations, the destination operand should be a MMX register, the source operand can be a MMX register or bit memory location.
The AMD64 and EM64T architectures we will use the common name x for them both extend the x86 instruction set for the bit processing.
While legacy and compatibility modes use the same set of registers and instructions, the new long mode extends the x86 operations to 64 bits and introduces several new registers. You can turn on generating the code for this mode with the use64 directive. Each of the general purpose registers is extended to 64 bits and the eight whole new general purpose registers and also eight new SSE registers are added. See table 2. The general purpose registers of smallers sizes are the low order portions of the larger ones.
You can still access the ah , bh , ch and dh registers in long mode, but you cannot use them in the same instruction with any of the new registers. In general any instruction from x86 architecture, which allowed bit or bit operand sizes, in long mode allows also the bit operands.
The bit registers should be used for addressing in long mode, the bit addressing is also allowed, but it's not possible to use the addresses based on bit registers.
Below are the samples of new operations possible in long mode on the example of mov instruction:. The long mode uses also the instruction pointer based addresses, you can specify it manually with the special RIP register symbol, but such addressing is also automatically generated by flat assembler, since there is no bit absolute addressing in long mode. You can still force the assembler to use the bit absolute addressing by putting the dword size override for address inside the square brackets.
There is also one exception, where the bit absolute addressing is possible, it's the mov instruction with one of the operand being accumulator register, and second being the memory operand. To force the assembler to use the bit absolute addressing there, use the qword size operator for address inside the square brackets. When no size operator is applied to address, assembler generates the optimal form automatically. Also as the immediate operands for bit operations only the signed bit values are possible, with the only exception being the mov instruction with destination operand being bit general purpose register.
That is, you can't use. To be compatible with former assemblers, if the section of new-lc is absolute, as issues a warning, then pretends the section of new-lc is the same as the current subsection.
Because as tries to assemble programs in one pass, new-lc may not be undefined. If you really detest this restriction we eagerly await a chance to share your improved assembler.
Beware that the origin is relative to the start of the section, not to the start of the subsection. This is compatible with other people's assemblers.
When the location counter of the current subsection is advanced, the intervening bytes are filled with fill which should be an absolute expression. If the comma and fill are omitted, fill defaults to zero. The first expression which must be absolute is the number of low-order zero bits the location counter must have after advancement. Use this directive to declare the number of lines--and, optionally, the number of columns--to use for each page, when generating listings.
If you do not use. You may omit the comma and columns specification; the default width is columns. If you specify lines as 0 , no formfeeds are generated save those explicitly specified with.
For each bignum, it emits an 8-byte integer. If the bignum won't fit in 8 bytes, it prints a warning message; and just takes the lowest order 8 bytes of the bignum. The term "quad" comes from contexts in which a "word" is two bytes; hence quad -word for 8 bytes. Repeat the sequence of lines between the. Use subheading as the title third line, immediately after the title line when generating assembly listings.
This directive affects subsequent pages, as well as the current page if it appears within ten lines of the top of a page. Set the storage-class value for a symbol. This directive may only be used inside a.
Storage class may flag whether a symbol is static or external, or it may record further symbolic debugging information. Use the. This directive is only supported for targets that actually support arbitrarily named sections; on a. For COFF targets, the. Each flag is a single character. The following flags are recognized: b bss section uninitialized data n section is not loaded w writable section d data section r read-only section x executable section If no flags are specified, the default flags depend upon the section name.
If the section name is not recognized, the default will be for the section to be loaded and writable. If the optional argument to the.
For ELF targets, the. If the section name is not recognized, the default will be for the section to have none of the above flags: it will not be allocated in memory, nor writable, nor executable.
The section will contain data. For ELF targets, the assembler supports another type of. There may be a sequence of comma separated flags: alloc section is allocatable write section is writable execinstr section is executable.
This changes symbol 's value and type to conform to expression. If symbol was flagged as external, it remains flagged see section Symbol Attributes. If you. In some configurations, however,.
This directive emits size bytes, each of value fill. Both size and fill are absolute expressions. If the comma and fill are omitted, fill is assumed to be zero. Warning: In most versions of the GNU assembler, the directive. All emit symbols see section Symbols , for use by symbolic debuggers. The symbols are not entered in the as hash table: they cannot be referenced elsewhere in the source file. Up to five fields are required:. If a warning is detected while reading a.
This is compatible with earlier assemblers! Copy the characters in str to the object file. You may specify more than one string to copy, separated by commas. Unless otherwise specified for a particular machine, the assembler marks the end of each string with a 0 byte. You can use any of the escape sequences described in section Strings. This is only supported on ELF platforms, and is typically used when assembling files to be linked into a shared library.
There are cases where it may make sense to use this in objects to be bound into an application itself so as to override a versioned symbol from a shared library. The name2 part of the name is the actual name of the symbol by which it will be externally referenced. The name name itself is merely a name of convenience that is used so that it is possible to have definitions for multiple versions of a function within a single source file, and so that the compiler can unambiguously know which version of a function is being mentioned.
The nodename portion of the alias should be the name of a node specified in the version script supplied to the linker when building a shared library. If you are attempting to override a versioned symbol from a shared library, then nodename should correspond to the nodename of the symbol you are trying to override.
Tags are used to link structure definitions in the symbol table with instances of those structures. Tells as to assemble the following statements onto the end of the text subsection numbered subsection , which is an absolute expression. If subsection is omitted, subsection number zero is used. Use heading as the title second line, immediately after the source file name and pagenumber when generating assembly listings.
This directive, permitted only within. This directive expects zero or more expressions , of any section, separated by commas. The articles in this section of the documentation provide reference material for the Microsoft ARM assembler armasm and related tools. The armasm assembler that the ARM Developer website describes isn't the same as the Microsoft armasm assembler that's included in Visual Studio and is documented in this section.
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